PCIe 3.0 Controller IP

The PCI Express 3.0 Controller IP Core provides a high-bandwidth and high-reliability soft-core solution for PCIe controllers. It supports multiple link speed and link width configurations to meet application requirements in different scenarios. The IP core's physical layer interface complies with the PIPE 3.0 protocol standard, and the transmit/receive equalization interface is compatible with Xilinx PCIe PHY IP v1.0.

Technical Advantages

• Flexible User Interfaces: AXI Stream interface or AXI Memory Mapped interface

• Ultra-Low Resource Utilization: Resource usage of PCIe 3.0 x8 is less than 50k LUTs

• Standard PIPE Interface: Applicable to the full range of Xilinx FPGAs

• Detailed Development Materials: Comprehensive product manual and test guidelines

• Simulation/Test Support: Provision of simulation/test components and test project support

Key Features

• Supports two functional modes: Endpoint (EP) and Root Port (RP)

• Supports link speed configuration: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s (dynamic speed switching supported)

• Supports link width configuration: x1, x2, x4, x8 (dynamic bit-width switching not supported)

• Supports maximum payload size: 128B/256B/512B/1024B

• Interrupt support: Legacy, MSI, MSIx

• Supports PCIe extended functions: AER (Advanced Error Reporting), DSN (Downstream Port Containment), LTR (Latency Tolerance Reporting), TPH (Transaction Processing Hints) Requester, VSEC (Vendor-Specific Extended Capability)

• Supports PCIe power management: L0s, L1

• Physical layer interface: Complies with the PIPE 3.0 protocol standard

• 8 GT/s equalization interface: Compatible with Xilinx PCIe PHY IP v1.0

• User interface: AXI Stream interface or AXI Memory Mapped interface (extended via bridge IP)

• Supports full-duplex communication

• Transaction layer flow control: Total RX Buffer size is configurable, and each buffer type can be allocated based on application needs

• The link layer adopts a proprietary retransmission algorithm, enabling shared use of TX Buffer and Replay Buffer

• Flexible retransmission mechanism ensures fast and successful data retransmission

• Dual-clock design: Link-layer LCRC (Link Cyclic Redundancy Check) operates in the user clock domain (uclk), facilitating clock convergence

• MAC layer jitter reduction: 8b/10b encoding uses register chain calibration; 128b/130b encoding uses synchronous FIFO calibration

• AXI Memory Mapped Bridge support: Optional

PHY Compatibility

Supports Xilinx PCIe PHY. For 7-series FPGAs operating at 8.0 GT/s, integration of a third-party 128b/130b soft PCS (Physical Coding Sublayer) is required.

Application Scope

Supports data computing and data transmission applications, and is particularly suitable for scenarios requiring high performance, low cost, easy upgrade & maintenance, and high reliability, including:

• Plug-in computing cards

• Chip-to-chip direct connection cards

• Network interface cards (NICs)

• Wired/wireless communication cards

• Data communication networks

• Wireless communication networks

Structural Diagram

(Note: Diagram content to be supplemented based on actual design)

Resource Utilization

Table A-1. Synthesis Resource Estimation (Vivado 2020.2)

Table A-2. PCIe 3.0 Controller Test Latency/Throughput using AXI Master

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Note: Test results are affected by link stability. For example, unstable power supply during data transmission may cause LCRC verification errors, triggering link replay and thus significantly impacting performance.

Implementation Example A: 3.0 x8

PCIe 3.0 RP

• Maximum payload size: 1024B

• Link speed: 8.0 GB/s; Link width: x8

• Integrated PCIe AXI Memory Mapped Bridge

• Implemented device: Alinx Z19 - Xilinx xczu19eg - ffvc1760 - 2 - i

PCIe 3.0 EP

• Maximum payload size: 1024B

• Link speed: 8.0 GB/s; Link width: x8

• Integrated PCIe AXI Memory Mapped Bridge

• Implemented device: Milianke MZU07A - Xilinx xczu7eg - ffvc1156 - 2 - i

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The application layer uses AXI Master IP.

Technical Characteristics

• Optimized for FPGA applications with low resource utilization

• Optimized timing paths for easier clock convergence

• AXI Stream data interface (without AXI Memory Mapped Bridge)

• AXI4 data interface (with AXI Memory Mapped Bridge)

• Proprietary link-layer retransmission algorithm with low RAM resource consumption

• Proprietary link-layer CRC operation structure, facilitating clock convergence in FPGA designs

• Configurable flow control size; each type of flow control can be allocated independently

• Optional services: AXI Memory Mapped Bridge

• Optional services: AXI Master/DMA Test IP

Standard Interface Protocols

• PCI Express Protocol

• NVM Express Protocol

Technical Support

Free technical support is provided for 6 working months from the delivery date, including telephone consultation and email consultation. The response time for technical issues shall not exceed 3 working days.

Functional and Timing Verification

Before release, the IP core has undergone extensive simulation and necessary FPGA verification.

Licensed Content

IP core licensing methods and technical documents include:

• FPGA netlist (EDIF)

• Complete simulation or test platform

• Synthesis scripts

• Technical documents such as user manuals and test reports

• Software drivers and test routines

• FPGA project examples